This invention relates to a semiconductor memory device including memory cells each comprised of one transistor and one capacitor and a peripheral circuit comprised of transistors and adapted to drive the memory cell.
In a conventional one-transistor/one-capacitor type dynamic memory cell, for example, it is known that a polysilicon or metal silicide is used as a material for a bit line which is connected through a contact hole to a source or drain region of a MOS transistor in the respective cell. The arrangement and manufacture of this type of memory cells will now be explained below with reference to FIG. 1.
Field oxide film 1 is formed on the surface of p type silicon substrate 2 and then selectively removed to expose part of the surface of substrate 2. Capacitor oxide films 3A, 3B and capacitor electrodes 4A, 4B are sequentially formed in that order on predetermined areas of the exposed surface of the substrate. In this way capacitor sections are formed which comprise capacitor electrodes 4A, 4B, capacitor oxide films 3A, 3B and substrate 2.
Then, interlayer insulating film 5 is formed on capacitor electrodes 4A, 4B; and gate oxide films 6A, 6B and transfer gate electrodes 7A, 7B are sequentially formed on those areas of the surface of substrate 2 where no capacitor section is formed. With capacitor electrodes 4A, 4B and transfer gate electrodes 7A, 7B as masks, an n type impurity is doped by an ion implantation method into substrate 2 to form n.sup.+ type impurity regions 8A, 8B, 8C for a source and drain. Insulating layer 9 is formed on the whole surface of the resultant structure, and contact hole 10 is formed in insulating layer 9 to partially expose n.sup.+ type impurity region 8C. Then, a polysilicon layer or metal silicide layer is formed on insulating film 9 and on the exposed surface of impurity region 8C. An n type impurity is doped into the polysilicon layer or metal silicide layer, followed by performing a heat treatment step to form high impurity concentration n.sup.++ type contact region 11. The resultant polysilicon layer or metal silicide layer is patterned to provide bit line 12. A semiconductor memory device is obtained in this way.
With an increase in dynamic memory capacity there is a tendency toward reducing an occupation area of a cell capacitor and, at the same time, thinning a capacitor oxide film to obtain a large cell capacitance.
FIG. 2 shows a memory device which is formed, taking into consideration a problem arising from the formation of a large-capacity dynamic memory. In this memory cell, n type regions 13A and 13B are formed in contact with n.sup.+ type regions 8A and 8B and beneath oxide films 3A and 3B, respectively. Furthermore, p.sup.+ type regions 14A and 14B are formed in contact with the undersurfaces of n type regions 13A and 13B. The formation of n type regions 13A, 13B causes an increase in impurity concentration level at those surface portions of substrate 2 situated beneath oxide films 3A, 3B. It is, therefore, possible to prevent a p type inversion layer or depletion layer from being formed beneath capacitor oxide films 3A, 3B when capacitor electrodes 4A, 4B are set at a certain potential level. This prevents a decrease in capacitance of the capacitor section including capacitor oxide films 3A, 3B.
In order to obtain the afore-mentioned effect the impurity concentration at the surface portions of n type regions 13A, 13B should be set at a high level of about 1.times.10.sup.18 to 1.times.10.sup.19 cm.sup.-3, though differing dependent upon the thickness of capacitor oxide films 3A, 3B as well as the potential at which capacitor electrodes 4A, 4B are set. p.sup.+ type regions 14A, 14B are formed to prevent an operation error resulting from a soft error which is a serious problem involved in a dynamic memory. p.sup.+ type regions 14A, 14B are formed such that they have an impurity concentration of approximately above 1.times.10.sup.17 cm.sup.-3 to permit a recombination, with holes, of electrons liberated from electron-hole pairs occurring in the substrate by an .alpha. ray.
In a memory device having the conventional dynamic memory cells as shown in FIGS. 1 and 2, an n.sup.+ type impurity is doped simultaneously into the source and circuit, not shown, for driving the memory cell array and into the source and drain regions of a transistor of each memory cell. Where contact is made between n.sup.+ type region 8C and the polysilicon layer or metal silicide layer for forming bit line 12, a natural oxide film is formed on the surface of n.sup.+ type region 8C at the contact section and acts as a barrier, failing to obtain better ohmic contact between bit line 12 and n.sup.+ type region 8C.
One solution to this problem is to perform a heat treatment step at above 1000.degree. C. for barrier breakage. With the recent trend toward the high integration density of elements and the consequent microminiaturization of gate electrodes and source and drain regions, if a high temperature heat treatment is conducted, the diffusion length of the source and drain regions becomes greater, causing a short channel effect and the resultant degradation in characteristics of transistors.
In the dynamic memory device as shown in FIG. 2, n.sup.+ type regions 8A and 8B contact p.sup.+ type regions 14A and 14B, respectively, for soft error prevention, thereby increasing a memory cell capacitance due to an increase in junction capacitance. However, the presence of the junction capacitance increases the number of generation/recombination centers and thus the leakage current, prominently reducing a pause time on which emphasis is placed in the dynamic memory.